There is ongoing work to enhance computer system performance, e.g., by increasing processing speed. Central processing units (CPUs) having multiple processing cores are now being developed to increase the processing speeds of high-end server computers, and even other computing devices. Multi-core processors are commercially available with at least two processing cores and a shared bus interface. Configuration and status registers are provided for each processing core, but the processing cores may also need access to shared configuration and status registers in the bus interface.
In an exemplary implementation, the shared configuration and status registers are mapped to a memory address range on the system bus and the processing cores may access the shared configuration and status registers by issuing transactions over the system bus. Software is provided to handle access operations for both the core registers and the common registers. In addition, the software has to arbitrate access to the common registers to prevent simultaneous writes by both processing cores. Such an approach is relatively slow.